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White Electronic Designs
WEDPS512K32V-XBX
512Kx32 SRAM 3.3V MULTI-CHIP PACKAGE
FEATURES
Access Times of 12, 15, 17, 20ns Packaging * 143 PBGA, 16mm x 18mm, 288mm2 Organized as 512Kx32; User Configurable as 1Mx16 or 2Mx8 Commercial, Industrial and Military Temperature Ranges Low Voltage Operation: * 3.3V 10% Power Supply
This product is subject to change without notice.
Low Power Data Retention 'L' Option TTL Compatible Inputs and Outputs Fully Static Operation: * No clock or refresh required. Three State Output.
PIN CONFIGURATION FOR WEDPS512K32V-XBX Top View
1 A B C D E F G H J K L M CS2# D9 D10 WE2# GND VCC CS1# D1 D2 WE1# GND 2 A2 A3 D8 D11 GND GND VCC VCC D0 D3 A6 A7 3 A1 A4 NC GND GND GND VCC VCC VCC NC A5 A8 4 A0 D14 D12 GND GND GND VCC VCC VCC D7 D6 A9 5 GND D15 D13 GND GND GND VCC VCC VCC D5 D4 vcc 6 GND NC GND GND GND GND VCC VCC VCC VCC NC vcc 7 VCC CS4# VCC VCC VCC VCC GND GND GND GND WE3# GND 8 VCC D24 D26 VCC VCC VCC GND GND GND D17 D19 GND 9 A18 D25 D27 VCC VCC VCC GND GND GND D16 D18 A10 10 A17 OE# WE4# VCC VCC VCC GND GND GND CS3# A14 A11 11 A16 A15 D31 D28 VCC VCC GND GND D23 D20 A13 A12 12 GND NC D30 D29 NC VCC GND NC D22 D21 NC vcc
Pin Description
I/O0-31 A0-18 WE1-4# CS1-4# OE# VCC GND NC Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground Not Connected
8 WE1# CS1# OE# A0-18
Block Diagram
WE2# CS2# WE3# CS3# WE4# CS4#
512K X 8
512K X 8
512K X 8
512K X 8
8
8
8
I/O0 - 7
I/O8 - 15
I/O16 - 23
I/O24 - 31
June 2004 Rev. 5
1
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter Operating Temperature Storage Temperature Signal Voltage Relative to GND Junction Temperature Supply Voltage Symbol TA TSTG VG TJ VCC Min -55 -65 -0.5 -0.5 Max +125 +150 4.6 150 4.6 Unit C C V C V CS# H L L L OE# X L X H WE# X H L H
WEDPS512K32V-XBX
TRUTH TABLE
Mode Standby Read Write Out Disable Data I/O High Z Data Out Data In High Z Power Standby Active Active Active
BGA THERMAL RESISTANCE
Parameter
Junction to Ball Junction to Case (Top)
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 3.0 2.2 -0.3 Max 3.6 VCC + 0.3 +0.8 Unit V V V
Symbol Theta JB Theta JC
Junction to Ambient (No Airflow) Theta JA
Max 16.9 11.3 9.8
Unit C/W C/W C/W
Note 1 1 1
NOTE: Refer to Application Note "PBGA Thermal Resistance Correlation" at www.wedc.com in the application notes section for modeling conditions.
CAPACITANCE
Ta = +25C Parameter OE# capacitance WE1-4# capacitance CS1-4# capacitance Data I/O capacitance Address input capacitance Symbol COE CWE CCS CI/O CAD Conditions VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VI/O = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz Max 30 10 10 10 30 Unit pF pF pF pF pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
VCC = 3.3V 0.3V, -55C TA +125C Parameter Input Leakage Current Output Leakage Current Operating Supply Current (x 32 Mode) Standby Current Output Low Voltage Output High Voltage Symbol ILI ILO ICC x 32 ISB VOL VOH Conditions VIN = GND to VCC CS# = VIH, OE# = VIH, VOUT = GND to VCC CS# = VIL, OE# = VIH, f = 5MHz, VCC = 3.6V CS# = VIH, OE# = VIH, f = 5MHz, VCC = 3.6V IOL = 4.0mA IOH = -4.0mA Min Max 10 10 400 120 0.4 Units A A mA mA V V
2.4
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V. Contact factory for low power option.
DATA RETENTION CHARACTERISTICS (WEDPS512K32LV-XBX only)
-55C TA +125C Parameter Data Retention Voltage Data Retention Current
June 2004 Rev. 5
Symbol VCC ICCDR
Conditions VCC = 2.19V CS = VCC - 0.2V
2
Min 2.19
Max
Units V
8.0
mA
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
AC CHARACTERISTICS
VCC = 3.3V, -55C TA +125C Parameter Read Cycle Read Cycle Time Address Access Time Output Hold from Address Change Chip Select Access Time Output Enable to Output Valid Chip Select to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z
1. This parameter is guaranteed by design but not tested.
WEDPS512K32V-XBX
Symbol tRC tAA tOH tACS tOE tCLZ1 tOLZ1 tCHZ1 tOHZ1 Min 12 0
-12 Max 12 0 12 7 1 0 7 7 1 0 Min 15
-15 Max 15 0 15 8 1 0 8 8 Min 17
-17 Max 17 0 17 8 1 0 8 8 Min 20
-20 Max 20 20 10
Units ns ns ns ns ns ns ns ns ns
10 10
AC CHARACTERISTICS
VCC = 3.3V, -55C TA +125C Parameter Write Cycle Write Cycle Time Chip Select to End of Write Address Valid to End of Write Data Valid to End of Write Write Pulse Width Address Setup Time Address Hold Time Output Active from End of Write Write Enable to Output in High Z Data Hold Time
1. This parameter is guaranteed by design but not tested.
Symbol Min tWC tCW tAW tDW tWP tAS tAH tOW1 tWHZ1 tDH 12 10 10 8 10 0 0 2
-12 Max Min 15 12 12 9 12 0 0 2 7 0 0
-15 Max Min 17 12 12 9 14 0 0 3 8 0
-17 Max Min 20 14 14 10 14 0 0 3 8 0
-20 Max
Units ns ns ns ns ns ns ns ns ns ns
9
FIGURE 4 - AC TEST CIRCUIT AC Test Conditions
IOL Current Source
Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level
VZ 1.5V (Bipolar Supply)
Typ VIL = 0, VIH = 3.0 5 1.5 1.5
Unit V ns V V
D.U.T. Ceff = 50 pf
IOH Current Source
Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 . VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.
June 2004 Rev. 5
3
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WEDPS512K32V-XBX
TIMING WAVEFORM - READ CYCLE
CS#
OE#
READ CYCLE 2, (CS# = OE# = VIL, WE# = VIH)
READ CYCLE 2 (WE# = VIH)
WRITE CYCLE - WE# CONTROLLED
CS#
WE#
WRITE CYCLE 1, WE# CONTROLLED
WRITE CYCLE - CS# CONTROLLED
CS#
WE#
WRITE CYCLE 2, CS# CONTROLLED
June 2004 Rev. 5
4
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WEDPS512K32V-XBX
PACKAGE 756: 143 BALL GRID ARRAY
BOTTOM VIEW
12 11 10 9 8 7 6 54 3 2 1 A B C
16.25 (0.640) MAX 13.97 (0.550) BSC 1.27 (0.050) BSC
D E F G H J K L M
1.27 (0.050) BSC 13.97 (0.550) BSC 18.25 (0.719) MAX
0.61 (0.024) BSC 1.93 (0.076) MAX
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
June 2004 Rev. 5
5
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ORDERING INFORMATION
WEDPS512K32V-XBX
WED P S 512K 32 L V - XX X X WHITE ELECTRONIC DESIGNS CORP. PLASTIC SRAM ORGANIZATION, 512Kx32 User configurable as 1Mx16 or 2Mx8 OPTIONS: L = Low power data retention Low Voltage Supply 3.3V 10% ACCESS TIME (ns) PACKAGE TYPE: B = 143 PBGA, 16mm x 18mm, 288mm2 DEVICE GRADE: M = MILITARY SCREENED -55C TO +125C I = INDUSTRIAL -40C TO 85C C = COMMERCIAL 0C TO +70C
June 2004 Rev. 5
6
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
512K x 32 SRAM PBGA Multi-Chip Package
WEDPS512K32V-XBX
Revision History Rev #
Rev 0 Rev 1
History
Initial Release Changes (Pg. 1) 1.1 Switch Rows and Columns header position
Release Date
March 2002 March 2002
Status
Advanced Advanced
Rev 2
Changes (Pg. 1) 2.1 Switch Rows and Columns header position (Pg. 1)
May 2002
Advanced
Rev 3
Changes (Pg. 1, 5) 3.1 Remove excess white space from package drawing for to create a consistent accurate style.
May 2002
Advanced
Rev 4
Changes (Pg. 1, 2, 7) 4.1 Add Thermal Resistance Table 4.2 Change product status to Final
January 2003
Final
Rev 5
Changes (Pg. 1, 2, 6, 7) 5.1 Add low power data retention option
June 2004
Final
June 2004 Rev. 5
7
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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